Dynamic integrated circuit memories such as a dynamic random access memory (DRAM) traditionally stores data as a charge on a memory cell capacitor. For example, a logical "one" is stored as a potential on the capacitor and a logical "zero" is represented by an uncharged capacitor. Because of the dense population of memory cells in an integrated circuit, the capacitance of each memory cell is small and the available charge is proportionally small. To read data from the memory cells, therefore, the charge must be sensed and amplified.
Typical memory circuits are designed to have pairs of data lines selectively coupled to the memory cells. The data line pairs are pre-charged to an equal potential between ground and the supply potential. When a memory cell is coupled to one of the data lines, a differential voltage is established between the data line pairs. A n-channel sense amplifier is used to detect the differential voltage and pull the low data line to ground. Likewise, a p-channel sense amplifier is used to detect the differential and drive the high data line to the supply voltage. As stated, the DRAM memory cell is dynamic, and as such the data must be periodically refreshed by writing back the data to the memory cell. To extend the period between write back, the initial charge stored on the memory cell should be provided using the maximum available potential voltage. Further, sense amplifiers are often shared between many memory cells to reduce the number of amplifiers needed for a memory circuit. Problem arise, however, in sharing the p-sense amplifiers. To maintain a maximum charging potential during the memory cell refresh, the p-sense amplifier must be coupled directly to the memory cell, or by using a transistor having a pumped gate voltage which is a threshold level above the supply voltage. Additional circuitry and current must, therefore, be provided to source the pumped gate voltage.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory circuit capable of complete write back operations using shared sense amplifiers without requiring a pumped voltage.